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dc.contributor.authorKer, MDen_US
dc.contributor.authorTsai, CSen_US
dc.date.accessioned2014-12-08T15:26:15Z-
dc.date.available2014-12-08T15:26:15Z-
dc.date.issued2003en_US
dc.identifier.isbn0-7803-7761-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/18647-
dc.description.abstractThis paper presents a 2.5V/5V mixed-voltage CMOS I/O buffer that does not need a CMOS technology with a dual-oxide option and complex bias circuits. The proposed mixed-voltage I/O buffer with simpler circuit structure can overcome the problems of leakage current and gate-oxide reliability, which occurring in the conventional CMOS I/O buffer. In this work, the new proposed design has been realized in a 0.25-mum CMOS process, but it can be easily scaled toward 0.18-mum or 0.15-mum processes to serve a 1.8V/3.3V mixed-voltage I/O interface.en_US
dc.language.isoen_USen_US
dc.titleDesign of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuiten_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V: BIO-MEDICAL CIRCUITS & SYSTEMS, VLSI SYSTEMS & APPLICATIONS, NEURAL NETWORKS & SYSTEMSen_US
dc.citation.spage97en_US
dc.citation.epage100en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000184904800025-
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