Quality-aware memory controller for multimedia platform SOC

Abstract

The ongoing advancements in VLSI technology allow SoC design to integrate heterogeneous control and computing functions into a single chip. On the other hand, the pressures of area and cost lead to the requirement for a single, shared off-chip DRAM memory subsystem. To satisfy different memory access requirements for latency and bandwidth of these heterogeneous functions to this kind of DRAM memory subsystem, a quality-aware memory controller is important. This paper presents an efficient memory controller that contains a quality-aware scheduler and a configurable DRAM memory interface socket to achieve high DRAM utilization while still meet different requirements for bandwidth and latency. Simulation results show that the latency of the latency-sensitive data flow can be reduced to 50%, and the memory bandwidths can be precisely allocated to bandwidth-sensitive data flows with a high degree of control.