標題: | An effective physical synthesis technique for multiplier |
作者: | Wang, CY Yang, YC Jon, JY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2003 |
摘要: | This paper presents an effective multiplier synthesis algorithm for cell-based multipliers. By using a novel tree generation algorithm with timing consideration for each vertical compressor slice(VCS), our synthesizer generates multipliers automatically with very promising results. |
URI: | http://hdl.handle.net/11536/18714 |
ISBN: | 0-7803-7765-6 |
期刊: | 2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS |
起始頁: | 192 |
結束頁: | 195 |
顯示於類別: | 會議論文 |