標題: Layout design of high-quality SOI varactor
作者: Chen, HY
Chen, KM
Huang, GW
Huang, CH
Yang, TH
Chang, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2003
摘要: This paper presents the geometry effect on the characteristics of accumulation type SOI varactor with Mesa-isolation technology. Constant gate area varactors with various geometry condition were implemented to investigate the effects of layout design parameters on overall varactor performance. Physical and mathematic analysis based on the measurement results show that parasitic capacitance at the edge of active region seriously degrads the device quality factor at smallest gate length. The optimized SOI varactor has a quality factor Q of about 150 /GHz/pF at medium gate length varactor. The experiment result can serve as a design reference for high-quality SOI varactors.
URI: http://hdl.handle.net/11536/18716
ISBN: 0-7803-7765-6
期刊: 2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS
起始頁: 273
結束頁: 275
顯示於類別:會議論文