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dc.contributor.authorWu, CYen_US
dc.contributor.authorChou, CYen_US
dc.date.accessioned2014-12-08T15:26:22Z-
dc.date.available2014-12-08T15:26:22Z-
dc.date.issued2003en_US
dc.identifier.isbn4-89114-034-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/18718-
dc.description.abstractA 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0.18um CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.en_US
dc.language.isoen_USen_US
dc.titleA 5-GHz CMOS double-quadrature receiver for IEEE 802.11a applicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERSen_US
dc.citation.spage149en_US
dc.citation.epage152en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000185582200039-
Appears in Collections:Conferences Paper