A 5-GHz CMOS double-quadrature receiver for IEEE 802.11a applications

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Wu, CY	en_US
dc.contributor.author	Chou, CY	en_US
dc.date.accessioned	2014-12-08T15:26:22Z	-
dc.date.available	2014-12-08T15:26:22Z	-
dc.date.issued	2003	en_US
dc.identifier.isbn	4-89114-034-8	en_US
dc.identifier.uri	http://hdl.handle.net/11536/18718	-
dc.description.abstract	A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0.18um CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.	en_US
dc.language.iso	en_US	en_US
dc.title	A 5-GHz CMOS double-quadrature receiver for IEEE 802.11a applications	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS	en_US
dc.citation.spage	149	en_US
dc.citation.epage	152	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000185582200039	-
顯示於類別：	會議論文