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dc.contributor.authorWang, THen_US
dc.contributor.authorTsai, CWen_US
dc.contributor.authorChen, MCen_US
dc.contributor.authorChan, CTen_US
dc.contributor.authorChiang, HKen_US
dc.contributor.authorLu, SHen_US
dc.contributor.authorHu, HCen_US
dc.contributor.authorChen, TFen_US
dc.contributor.authorYang, CKen_US
dc.contributor.authorLee, MTen_US
dc.contributor.authorWu, DYen_US
dc.contributor.authorChen, JKen_US
dc.contributor.authorChien, SCen_US
dc.contributor.authorSun, SWen_US
dc.date.accessioned2014-12-08T15:26:23Z-
dc.date.available2014-12-08T15:26:23Z-
dc.date.issued2003en_US
dc.identifier.isbn0-7803-7649-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/18730-
dc.description.abstractNegative substrate bias enhanced breakdown hardness in ultra-thin oxide (1.4nm) pMOS is observed. This result is believed due to the increase of hole stress current during breakdown progression via breakdown induced carrier heating. Numerical analysis of substrate bias effect on hole tunneling current is performed to support the proposed theory. This phenomenon is particularly significant to gate oxide reliability in floating substrate (PD-SOI) or forward-biased substrate devices.en_US
dc.language.isoen_USen_US
dc.titleNegative substrate bias enhanced breakdown hardness in ultra-thin oxide pMOSFETsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal41ST ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUMen_US
dc.citation.spage437en_US
dc.citation.epage441en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000182322300076-
顯示於類別：會議論文


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