Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed-voltage I/O interface circuits

Abstract

A novel electrostatic discharge (TSD) implantation method is proposed to significantly improve machine-model (MM) ESD robustness of NMOS device in stacked configuration (stacked NMOS). By using this ESD implantation method, the ESD current is discharged far away from the surface channel of NMOS, therefore the stacked NMOS in the mixed-voltage I/O interface can sustain a much higher ESD level, especially under the MM ESD stress. The MM ESD robustness of the stacked NMOS with a device dimension of W/L=300mum/0.5 mum for each NMOS has been successfully improved from the original 358 V to become 491 V in a 0.25-mum CMOS process. This ESD implantation, method with the n-type impurity is fully process-compatible to general sub-quarter-micron CMOS processes.