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dc.contributor.authorHuang, SRen_US
dc.contributor.authorDung, LRen_US
dc.date.accessioned2014-12-08T15:26:27Z-
dc.date.available2014-12-08T15:26:27Z-
dc.date.issued2002en_US
dc.identifier.isbn0-7695-1486-3en_US
dc.identifier.issn2159-3477en_US
dc.identifier.urihttp://hdl.handle.net/11536/18776-
dc.description.abstractThis paper presents a VLSI design methodology for the MAC-level DWT processor based on a novel limited-resource scheduling (LRS) algorithm. The r-split Fully-specified Signal Flow Graph (FSFG) of limited-resource FIR filter has been developed for the scheduling of the MAC-level DWT signal processing. Given a set of architecture constraints and DWT parameters, the LRS algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation, and the performance has also been investigated. Because the registers of FIR filtering are reused for the inter-octave storage, the MAC-level DWT architecture may require less extra inter-octave memory than the traditional architecture.en_US
dc.language.isoen_USen_US
dc.titleVLSI implememtation for MAC-level DWT architectureen_US
dc.typeProceedings Paperen_US
dc.identifier.journalISVLSI 2000: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI - NEW PARADIGMS FOR VLSI SYSTEMS DESIGNen_US
dc.citation.spage101en_US
dc.citation.epage106en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000176274900017-
Appears in Collections:Conferences Paper