完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Jiang, TY | en_US |
dc.contributor.author | Liu, CNJ | en_US |
dc.contributor.author | Jou, JY | en_US |
dc.date.accessioned | 2014-12-08T15:26:28Z | - |
dc.date.available | 2014-12-08T15:26:28Z | - |
dc.date.issued | 2002 | en_US |
dc.identifier.isbn | 0-7695-1825-7 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18787 | - |
dc.description.abstract | We propose an effective approach to diagnose multiple design errors in HDL designs with only one erroneous test case. Error candidates will be greatly reduced while ensuring that true erroneous statements are included in, The probability of correctness for each potential erroneous statement will be estimated such that the most suspected statements are reported first. Experiments show that the size of error candidates is indeed small and the estimation for the probability of correctness for potential error candidates is accurate. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Effective error diagnosis for RTL designs in HDLS | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE 11TH ASIAN TEST SYMPOSIUM (ATS 02) | en_US |
dc.citation.spage | 362 | en_US |
dc.citation.epage | 367 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000179973300061 | - |
顯示於類別: | 會議論文 |