完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Ker, MD | en_US |
dc.contributor.author | Hsu, KC | en_US |
dc.date.accessioned | 2014-12-08T15:26:29Z | - |
dc.date.available | 2014-12-08T15:26:29Z | - |
dc.date.issued | 2002 | en_US |
dc.identifier.isbn | 0-7803-7494-0 | en_US |
dc.identifier.issn | 1063-0988 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18807 | - |
dc.description.abstract | The turn-on mechanism of SCR device is essentially a current triggering event. While a current is applied to the base or substrate of a SCR device, it can be quickly triggered on into its latching state. In this paper, the complementary substrate-triggered SCR devices which are combined with the substrate-triggered technique and SCR devices, are first reported in the literature for using in the on-chip ESD. protection circuits. A complementary style on the substrate-triggered SCR devices is designed to discharge both of the positive and negative ESD stresses on the pad. The total holding voltage of the substrate-triggered SCR device can be increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices for the I/O pad and power pad have been successfully verified in a 0.25-mum STI CMOS process with the HBM (MM) ESD level of >8kV (650V) in a small layout area. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Complementary substrate-triggered SCR devices for on-chip ESD protection circuits | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS | en_US |
dc.citation.spage | 229 | en_US |
dc.citation.epage | 233 | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000179659500040 | - |
顯示於類別: | 會議論文 |