完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | SU, HP | en_US |
dc.contributor.author | LIU, HW | en_US |
dc.contributor.author | WANG, PW | en_US |
dc.contributor.author | CHENG, PW | en_US |
dc.contributor.author | JEN, IM | en_US |
dc.contributor.author | HONG, G | en_US |
dc.contributor.author | CHENG, HC | en_US |
dc.date.accessioned | 2014-12-08T15:03:21Z | - |
dc.date.available | 2014-12-08T15:03:21Z | - |
dc.date.issued | 1995-06-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/55.790725 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/1888 | - |
dc.description.abstract | A novel dielectric fabricated dy thermal oxidation of ultrathin rugged polysilicon film is proposed for nonvolatile memories, Different roughness degrees for the top and bottom interfaces of this dielectric ate detected by the atomic-force-microscopy (AFM) and high resolution transmission electron microscopy (HRTEM), Due to the microtips formed at the bottom interface of the dielectric, significant improvements in the high conduction efficiency, low trapping rate, good uniformity, and high reliability under positive gate-bias are obtained for the dielectric. Therefore, rugged polyoxide is promising for future 5-V-only floating-gate applications. | en_US |
dc.language.iso | en_US | en_US |
dc.title | NOVEL TUNNELING DIELECTRIC PREPARED BY OXIDATION OF ULTRATHIN RUGGED POLYSILICON FOR 5-V-ONLY NONVOLATILE MEMORIES | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/55.790725 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 16 | en_US |
dc.citation.issue | 6 | en_US |
dc.citation.spage | 250 | en_US |
dc.citation.epage | 252 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1995RA18200013 | - |
dc.citation.woscount | 3 | - |
顯示於類別: | 期刊論文 |