標題: A compact software-controlled clock multiplier for SoC application
作者: Chen, PL
Lee, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2002
摘要: A compact software-controlled clock multiplier for SoC application is presented in this paper. The control mechanism of clock multiplier includes frequency acquisition, phase acquisition and phase/frequency maintenance modes; these operations sequence are programmable. Our proposed clock multiplier is integrated with an 8-bit microcontroller in order to verify the proposed software-controlled mechanism. The control mechanism is sharing with the computing power of microcontroller. A proto-type chip has been implemented with 0.35 um 1P4M CMOS process that can operate from 25MHz to 80MHz. The multiplication factor can range from 2 to 128 and software instructions are less than 90 instructions. Thus it not only reduces the cost and design complexity of clock multiplier, but also offers particular advantages, especially when computing power is already available.
URI: http://hdl.handle.net/11536/18897
ISBN: 0-7803-7523-8
期刊: 2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS
起始頁: 499
結束頁: 502
Appears in Collections:Conferences Paper