可移植性數位控制式振盪器及動態頻率計數迴路之研究

Abstract

現代的系統單晶片(SoC)需要晶片內在的時脈產生器以及產生許多不同的頻率，來提供給其他子系統使用，一般常用鎖相迴路為基礎的時脈產生器來達成此任務。然而，鎖相迴路的迴路參數為了減少抖動量以及保持迴路的穩定度，因而必須依照輸出頻率以及頻率產生倍數來調整，現有類比電路的方式需要較長的設計週期。 本論文從可移植性數位控制式振盪器，動態取樣的迴路控制器，到利用串接式迴路來達成高倍數，提供一個實用的解決方式。具體而言，此種所提出架構的數位控制式振盪器利用反或閘/反及閘的寄生電容差值作為數位控制式壓控變容器，不同型式的數位控制式壓控變容器也加以討論比較。數位控制式壓控變容器能夠提升傳統標準細胞單元中單一緩衝器的時間延遲的極限，在微調上時間解析度能夠依照使用驅動細胞單元的能力及數位控制式壓控變容器的電容差異，作不同的選擇。同時具有較線性的時間解析度相對於使用OAI-AOI細胞單元或三態緩衝器矩陣，除此之外，電路佈局圖可以利用自動繞線及擺放的軟體工具完成。 本論文接著提出低成本的動態頻率計數迴路使用變動時間來估算及調整數位控制式振盪器的頻率，傳統相頻器以及可程式化除頻器被數位式比較器及數位控制式振盪器計數器取代，數位控制式振盪器計數器的值可再細分為商數向量及餘數向量，同時，使用臨界值的設立及動態性的取樣時間來解決計數器的取樣量化問題以及提高頻率偵測的解析度，提出的動態頻率計數迴路透過模擬比較及晶片功能驗證。 本論文最後發展串接式動態頻率計數迴路應用在高倍數及低輸入頻率的應用中，所提出的時脈產生器其倍數可從4 ~ 13888 (其中5122 cases)，其抖動量值小於輸出時脈週期的2.8%，最低的輸入頻率為19.26仟赫茲到最高輸入頻率為60百萬赫茲，其核心面積為0.16平方毫米(mm2)，當工作在1.8伏、378百萬赫茲時其消耗功率為15毫瓦，以上所提出的設計均使用高階應體描述語言，再使用標準細胞單元件庫來合成。提出高解析度之可移植性數位控制式振盪器、態頻率計數迴路和串接式動態頻率計數迴路在0.35微米或0.18微米的標準元件庫中驗證，此所提出的可移植性數位控制式振盪器、動態頻率計數迴路和串接式動態頻率計數迴路，十分適合在系統整合的應用及系統單晶片中。

Modern system-on-a-chip (SoC) processors often require on-chip clock generation and multiplication to produce several unrelated frequencies for other sub-systems. PLL-based clock generator is a common way of frequency multiplication to accomplish the task. However, the loop parameters must be adjusted to minimize jitter performance and insure stability for each output frequency and multiplication factors. Conventional analog skills suffer from long design cycle. This dissertation provides a practical solution, from portable digitally controlled oscillator (DCO), dynamic sampling algorithm for loop controller, and a cascaded loop for wide multiplication range. Specifically, the proposed DCO with novel digital controlled varactors (DCV) based on parasitic capacitance difference of NOR/NAND gates can enhance the timing limitations as compared with a single buffer cell. Different types of NOR/NAND gates (2-input or 3-input) for DCV are also investigated. The timing resolution in fine-tuned stage can be decided from different driving cells and capacitance difference of each DCV cell. Thus, a high resolution DCO with better timing linearity as compared with OAI-AOI cell or tri-state matrix is achieved. The final circuit layout can be generated using an auto placement and routing (APR) tools. We next propose a dynamic counting loop (DFC) with low cost that uses variable time period to estimate and tune the frequency DCO. Conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. Also, a threshold region is set and by using dynamic sampling period to solve the quantization effect of counter sampling and enhance resolution of frequency detection. The proposed algorithm was simulated and verified with test chips. Finally, we develop a cascaded DFC loops that can be applied in wide multiplication ranges applications with low input frequency. The proposed clock generator achieves a multiplication ranges from 4 to 13888 (with 5122 cases) with output peak-to-peak jitter less than 2.8% of clock period. The lowest input frequency is 19.26KHz and the maximum input frequency is 60MHz. A test chip for the proposed clock generator is fabricated in 0.18 mm CMOS process with core area of 0.16 mm2. Power consumption is 15 mW @ 378 MHz with 1.8 V supply voltage. The above designs are designed in gate-level Hardware Description Language (HDL) codes and synthesized for a target cell library. The proposed portable DCO, DFC loop, and a cascaded DFC loops have been verified on silicon using 0.35-mm or 0.18-mm CMOS cell library. As a result, the proposed portable DCO, DFC loop and cascaded DFC loops are well-suited for system-level integration and SoC applications.