標題: | Full current-mode techniques for high-speed CMOS SRAMs |
作者: | Wang, SM Wu, CK 交大名義發表 National Chiao Tung University |
公開日期: | 2002 |
摘要: | This paper describes an experimental 32Kx8 CMOS SRAM with a 9ns access time at a supply voltage of 3V using a 0.35um 1P2M CMOS logic technology. Based on the full current-mode techniques for read/write operation, the sensing speed and write pulse width are insensitive to the bit-line capacitance. Due to these techniques, the voltage swing at the bit-line and data-line can be kept quite small all the time. The active current is 28mA at 100MHz under typical conditions. |
URI: | http://hdl.handle.net/11536/18918 |
ISBN: | 0-7803-7448-7 |
期刊: | 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS |
起始頁: | 580 |
結束頁: | 582 |
顯示於類別: | 會議論文 |