Full metadata record
DC FieldValueLanguage
dc.contributor.authorKer, MDen_US
dc.contributor.authorChuang, CHen_US
dc.date.accessioned2014-12-08T15:26:38Z-
dc.date.available2014-12-08T15:26:38Z-
dc.date.issued2002en_US
dc.identifier.isbn0-7803-7448-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/18922-
dc.description.abstractOn-chip ESD protection circuits realized with novel diode structures without the field-oxide boundary across the p/n junction are proposed. A PMOS (NMOS) is especially inserted into the diode structure to form the PMOS-bounded (NMOS-bounded) diode, which is used to block the field oxide isolation across the p/n junction in the diode structure. Without the field oxide boundary across the p/n junction of diode structure, the proposed PMOS-bounded and NMOS-bounded diodes can sustain much higher ESD stress, especially under the reverse-biased condition. Such PMOS-bounded and NMOS-bounded diodes are fully process-compatible to general CMOS processes without additional process modification or mask layers. The ESD protection circuits designed by such new diodes with different junction perimeters have been successfully verified in a 0.35-mum CMOS process.en_US
dc.language.isoen_USen_US
dc.titleESD protection circuits with novel MOS-bounded diode structuresen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGSen_US
dc.citation.spage533en_US
dc.citation.epage536en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000186328700134-
Appears in Collections:Conferences Paper