Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ker, MD | en_US |
dc.contributor.author | Chuang, CH | en_US |
dc.date.accessioned | 2014-12-08T15:26:38Z | - |
dc.date.available | 2014-12-08T15:26:38Z | - |
dc.date.issued | 2002 | en_US |
dc.identifier.isbn | 0-7803-7448-7 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18922 | - |
dc.description.abstract | On-chip ESD protection circuits realized with novel diode structures without the field-oxide boundary across the p/n junction are proposed. A PMOS (NMOS) is especially inserted into the diode structure to form the PMOS-bounded (NMOS-bounded) diode, which is used to block the field oxide isolation across the p/n junction in the diode structure. Without the field oxide boundary across the p/n junction of diode structure, the proposed PMOS-bounded and NMOS-bounded diodes can sustain much higher ESD stress, especially under the reverse-biased condition. Such PMOS-bounded and NMOS-bounded diodes are fully process-compatible to general CMOS processes without additional process modification or mask layers. The ESD protection circuits designed by such new diodes with different junction perimeters have been successfully verified in a 0.35-mum CMOS process. | en_US |
dc.language.iso | en_US | en_US |
dc.title | ESD protection circuits with novel MOS-bounded diode structures | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS | en_US |
dc.citation.spage | 533 | en_US |
dc.citation.epage | 536 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000186328700134 | - |
Appears in Collections: | Conferences Paper |