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dc.contributor.authorLiu, HCen_US
dc.contributor.authorLin, YHen_US
dc.contributor.authorChou, BCSen_US
dc.contributor.authorHsu, YYen_US
dc.contributor.authorHsu, WSen_US
dc.date.accessioned2014-12-08T15:26:42Z-
dc.date.available2014-12-08T15:26:42Z-
dc.date.issued2001en_US
dc.identifier.isbn0-8194-4322-0en_US
dc.identifier.issn0277-786Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/18979-
dc.identifier.urihttp://dx.doi.org/10.1117/12.449008en_US
dc.description.abstractIn ICP-RIE process, there have been many investigations on etching rate. However, only few published reports mentioned the sidewall roughness, which is a critical issue for optical devices. Here, experimental investigations about fabrication parameters in the STS Advanced Silicon Etch (ASE) process for sidewall roughness are performed. In our experiments, the photoresist of AZ1500 is used, and several parameters in the ASE process like over time, ramping time, Ar flow rate, platen power, and etching cycle time have been systematically studied. It is found that sidewall mean roughness can be down to 9.11 nm at etching rate of 2.5 mum/min. Comparing with other published works at similar sidewall roughness (around 10 nm), our experimental data have the highest etching rate. For the same STS ICP-RIE systems, our data have smallest sidewall roughness, comparing to previous literatures.en_US
dc.language.isoen_USen_US
dc.titleParameters study to improve sidewall roughness in Advanced Silicon Etch processen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1117/12.449008en_US
dc.identifier.journalDEVICE AND PROCESS TECHNOLOGIES FOR MEMS AND MICROELECTRONICS IIen_US
dc.citation.volume4592en_US
dc.citation.spage503en_US
dc.citation.epage513en_US
dc.contributor.department機械工程學系zh_TW
dc.contributor.departmentDepartment of Mechanical Engineeringen_US
dc.identifier.wosnumberWOS:000174910000058-
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