完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | Ker, MD | en_US |
| dc.contributor.author | Chuang, CH | en_US |
| dc.date.accessioned | 2014-12-08T15:26:45Z | - |
| dc.date.available | 2014-12-08T15:26:45Z | - |
| dc.date.issued | 2001 | en_US |
| dc.identifier.isbn | 0-7803-6675-1 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/19014 | - |
| dc.language.iso | en_US | en_US |
| dc.title | ESD implantations in 0.18-mu m salicided CMOS technology for on-chip ESD protection with layout consideration | en_US |
| dc.type | Proceedings Paper | en_US |
| dc.identifier.journal | PROCEEDINGS OF THE 2001 8TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS | en_US |
| dc.citation.spage | 85 | en_US |
| dc.citation.epage | 90 | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.identifier.wosnumber | WOS:000171369600012 | - |
| 顯示於類別： | 會議論文 | |
- ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technology / Ker, MD;Chuang, CH;Lo, WY
- Substrate-triggered ESD protection circuit without extra process modification / Ker, MD;Chen, TY
- ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness / Ker, MD;Hsu, HC;Peng, JJ
- Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process / Ker, MD;Chen, TY
- Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS process / Ker, MD;Chuang, CH;Lo, WY
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