Novel diode structures and ESD protection circuits in a 1.8-V 0.15-mu m partially-depleted SOI salicided CMOS process

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Ker, MD	en_US
dc.contributor.author	Hung, KK	en_US
dc.contributor.author	Tang, HTH	en_US
dc.contributor.author	Huang, SC	en_US
dc.contributor.author	Chen, SS	en_US
dc.contributor.author	Wang, MC	en_US
dc.date.accessioned	2014-12-08T15:26:45Z	-
dc.date.available	2014-12-08T15:26:45Z	-
dc.date.issued	2001	en_US
dc.identifier.isbn	0-7803-6675-1	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19016	-
dc.language.iso	en_US	en_US
dc.title	Novel diode structures and ESD protection circuits in a 1.8-V 0.15-mu m partially-depleted SOI salicided CMOS process	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	PROCEEDINGS OF THE 2001 8TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS	en_US
dc.citation.spage	91	en_US
dc.citation.epage	96	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000171369600013	-
顯示於類別：	會議論文