Socillator test: A delay test scheme for embedded ICs in the boundary-scan environment

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Tan, TJ	en_US
dc.contributor.author	Lee, CL	en_US
dc.date.accessioned	2014-12-08T15:26:47Z	-
dc.date.available	2014-12-08T15:26:47Z	-
dc.date.issued	2001	en_US
dc.identifier.isbn	0-7695-1123-6	en_US
dc.identifier.issn	1093-0167	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19041	-
dc.description.abstract	A novel test scheme, which uses an oscillation source to supply the test signal and a transition detector to detect the arrival of the transition of the test signal through the CUT within the specific delay rime, is proposed. The scheme is ideal to test embedded chips in the boundary scan environment within an SOC.	en_US
dc.language.iso	en_US	en_US
dc.subject	delay testing	en_US
dc.subject	embedded testing	en_US
dc.subject	SOC testing	en_US
dc.subject	oscillation test	en_US
dc.subject	system test	en_US
dc.title	Socillator test: A delay test scheme for embedded ICs in the boundary-scan environment	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	19TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS	en_US
dc.citation.spage	158	en_US
dc.citation.epage	162	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000169368600023	-
顯示於類別：	會議論文