NITRIDATION OF THE STACKED POLY-SI GATE TO SUPPRESS THE BORON PENETRATION IN PMOS

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	LIN, YH	en_US
dc.contributor.author	LAI, SC	en_US
dc.contributor.author	LEE, CL	en_US
dc.contributor.author	LEI, TF	en_US
dc.contributor.author	CHAO, TS	en_US
dc.date.accessioned	2014-12-08T15:03:22Z	-
dc.date.available	2014-12-08T15:03:22Z	-
dc.date.issued	1995-06-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/55.790724	en_US
dc.identifier.uri	http://hdl.handle.net/11536/1904	-
dc.description.abstract	Nitridation to create nitrogen-rich layers in-between the stacked layers of the poly-Si gate to suppress the boron penetration for pMOS with the gate BF (+)(2)-implantation is proposed and demonstrated, The MOS capacitors fabricated by using this nitridized stacked poly-Si gate have better thermal stability and much improved electrical characteristics.	en_US
dc.language.iso	en_US	en_US
dc.title	NITRIDATION OF THE STACKED POLY-SI GATE TO SUPPRESS THE BORON PENETRATION IN PMOS	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/55.790724	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	16	en_US
dc.citation.issue	6	en_US
dc.citation.spage	248	en_US
dc.citation.epage	249	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1995RA18200012	-
dc.citation.woscount	8	-
顯示於類別：	期刊論文

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