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dc.contributor.authorChen, SJen_US
dc.contributor.authorLin, CCen_US
dc.contributor.authorChung, SSen_US
dc.contributor.authorLin, HCen_US
dc.date.accessioned2014-12-08T15:26:48Z-
dc.date.available2014-12-08T15:26:48Z-
dc.date.issued2001en_US
dc.identifier.isbn0-7803-6412-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/19055-
dc.identifier.urihttp://dx.doi.org/10.1109/VTSA.2001.934476en_US
dc.description.abstractPlasma etching of poly-silicon gate in CMOS devices induces the plasma edge damage. This damage will be enhanced in the successive plasma processes. New experimental evidences of this effect will be examined in this study. Results have been verified for both surface channel nand p-MOSFETs. First, from the measurements of high-density antenna structures, this enhanced edge damage has been characterized by the charge-pumping (CP) profiling technique. Then, a 4-phase edge damage mechanism has been proposed. For the first time, it was found that a two-peak spatial distribution of the interface state was found near the device drain region. We call it (P) under bar lasma (C) under bar harging (E) under bar nhanced (H) under bar ot (C) under bar arrier (PCE-HC) effect. This enhanced damage effect will induce further device degradation, in particular for the scaled devices.en_US
dc.language.isoen_USen_US
dc.titleNew experimental evidences of the plasma charging enhanced hot carrier effect and its impact on surface channel CMOS devicesen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/VTSA.2001.934476en_US
dc.identifier.journal2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage33en_US
dc.citation.epage36en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000169941100009-
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