A new physical and quantitative width dependent hot carrier model for shallow-trench-isolated CMOS devices

Abstract

In this paper, we present new results on the width dependent hot-carrier (HC) degradation for shallow-trench-isolated (STI) CMOS devices. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. New models and mechanisms are proposed to explain the width dependent degradation for both n-channel and p-channel MOSFET's, where new monitors are developed for both types of devices respectively. In fi-MOSFET's, the interface state generation at the STI-edge is enhanced for narrow width device. However, for p-MOSFET's, a two-dimensional channel shortening model is introduced. The channel shortening induced oxide damage is the dominant mechanism for the drain current degradation. Both are found to be strongly related to the mechanical stress on the border of the trench. This is a very crucial issue for the present and future CMOS ULSI using STI technologies.