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dc.contributor.authorWang, MFen_US
dc.contributor.authorKao, YCen_US
dc.contributor.authorHuang, TYen_US
dc.contributor.authorLin, HCen_US
dc.contributor.authorChang, CYen_US
dc.date.accessioned2014-12-08T15:26:54Z-
dc.date.available2014-12-08T15:26:54Z-
dc.date.issued2001en_US
dc.identifier.isbn0-9651577-5-Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/19143-
dc.description.abstractThe effects of rapid-thermal annealing (RTA) after source/drain (S/D) implant on the characteristics of CMOS transistors with sputtered TiN gate were investigated. Our results indicate that n(+)/p junctions need higher thermal budget than p(+)/n junctions to achieve low leakage performance. It was also found fron C-V measurements that the flat-band voltage and oxide thickness are both affected by the annealing treatment, especially for p-channel devices. A hump in the subthreshold characteristics of p-channel transistors is observed, owing to the existence of a leakage path along the isolation edge. It is also shown that agglomeration phenomenon is easier to incur during the high-temperature RTA step as the metal gate width becomes narrower. When this happens, gate oxide integrity would be degraded, resulting in increased gate leakage of n-channel transistors.en_US
dc.language.isoen_USen_US
dc.titleThermal stability of PVD TiN gate and its impacts on characteristics of CMOS transistorsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2001 6TH INTERNATIONAL SYMPOSIUM ON PLASMA- AND PROCESS-INDUCED DAMAGEen_US
dc.citation.spage36en_US
dc.citation.epage39en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000169876700010-
Appears in Collections:Conferences Paper