完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wang, WT | en_US |
dc.contributor.author | Ker, MD | en_US |
dc.contributor.author | Chiang, MC | en_US |
dc.contributor.author | Chen, CH | en_US |
dc.date.accessioned | 2014-12-08T15:26:55Z | - |
dc.date.available | 2014-12-08T15:26:55Z | - |
dc.date.issued | 2001 | en_US |
dc.identifier.isbn | 0-7803-6412-0 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/19160 | - |
dc.description.abstract | Level shifters for 1.0-V to 3.3-V high-speed interfaces are proposed. Level-up shifter uses zero-Vt 3.3-V NMOSs as voltage clamps to protect 1.0-V NMOS switches from high voltage stress across the gate oxide. Level-down shifter uses 3.3-V NMOSs as both pull-up and pull-down devices with supply voltage of 1.0-V and gate voltage swing from 0-V to 3.3-V. The zero-Vt NMOS is a standard MOSFET device in a 0.13-mum CMOS process without adding extra mask or process step to realize it. Level-up transition from 0.9-V to 3.6-V takes only 1 ns in time, and the level-down transition has no minimum core voltage limitation. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Level shifters for high-speed 1-v to 3.3-v interfaces in a 0.13-mu m Cu-Interconnection/Low-k CMOS technology | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS | en_US |
dc.citation.spage | 307 | en_US |
dc.citation.epage | 310 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000169941100078 | - |
顯示於類別: | 會議論文 |