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dc.contributor.authorPan, SRen_US
dc.contributor.authorChang, YWen_US
dc.date.accessioned2014-12-08T15:27:03Z-
dc.date.available2014-12-08T15:27:03Z-
dc.date.issued2000en_US
dc.identifier.isbn0-7695-0801-4en_US
dc.identifier.issn1063-6404en_US
dc.identifier.urihttp://hdl.handle.net/11536/19261-
dc.description.abstractIn this paper, we propose a unified wire sizing and perturbation algo rithm for crosstalk-constrained performance optimization that is applicable to general routing structures. Our algorithm is based on a two-stage iterative technique: we first perturb all wires to the positions with the minimum delay, then we adjust the wire sizes to further optimize delay under crosstalk constraints. The unified wire sizing and perturbation technique has the property of unimodality, implying that there is a unique position resulting in the optimal delay and crosstalk. Applying these properties can dramatically reduce the search space and thus lead to a very efficient method to determine the best wire position and the optimal wire size. Experimental results show that our algorithm can achieve average improvements of 44.5% and 40.2% in delay without sacrificing area and crosstalk for the 0.18 mum and 0.25 mum process technologies, respectively. Further, we develop an effective incremental update technique that can substantially speed up the runtime. Empirically, this technique can reduce runtime by 10 times.en_US
dc.language.isoen_USen_US
dc.titleCrosstalk-constrained performance optimization by using wire sizing and perturbationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGSen_US
dc.citation.spage581en_US
dc.citation.epage584en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000165305100087-
Appears in Collections:Conferences Paper