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dc.contributor.authorLin, JWen_US
dc.contributor.authorLee, CLen_US
dc.contributor.authorSu, CCen_US
dc.contributor.authorChen, JEen_US
dc.date.accessioned2014-12-08T15:27:06Z-
dc.date.available2014-12-08T15:27:06Z-
dc.date.issued2000en_US
dc.identifier.isbn0-7695-0888-Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/19325-
dc.description.abstractThis paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into discrete signal flow graph, then constructs "diagnosing evaluators", which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power the OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as faults in OP's.en_US
dc.language.isoen_USen_US
dc.titleFault diagnosis for linear analog circuitsen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE NINTH ASIAN TEST SYMPOSIUM (ATS 2000)en_US
dc.citation.spage25en_US
dc.citation.epage30en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000166979100005-
顯示於類別:會議論文