完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen, C | en_US |
dc.contributor.author | Chang, CY | en_US |
dc.contributor.author | Chou, JW | en_US |
dc.contributor.author | Huang, CT | en_US |
dc.contributor.author | Lin, KC | en_US |
dc.contributor.author | Cheng, YC | en_US |
dc.contributor.author | Lin, CY | en_US |
dc.date.accessioned | 2014-12-08T15:27:07Z | - |
dc.date.available | 2014-12-08T15:27:07Z | - |
dc.date.issued | 2000 | en_US |
dc.identifier.isbn | 0-7803-6304-3 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/19349 | - |
dc.description.abstract | Excellent PMOS short channel effect is achieved by using high energy, large tilt angle arsenic implant as P-Halo. For the first time, it was found that the tail profile of P-Halo implant through the polysilicon gate, therefore, the channel concentration is modulated not only laterally from gate edge but also vertically from top of the polysilicon gate and it resulted in very flat short channel behavior. The effect of arsenic P-Halo implant was comprehensively studied and well characterized to explain this specific phenomenon. The gate oxide integrity was examined by Q(BD) and it passed the lifetime of 10 years at different conditions of P-Halo implants. Excellent performance of 0.12um PMOSFET is also demonstrated in this work. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Optimization of short channel effect by arsenic P-Halo implant through polysilicon gate for 0.12uw P-MOSFET | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2000 IEEE HONG KONG ELECTRON DEVICES MEETING, PROCEEDINGS | en_US |
dc.citation.spage | 44 | en_US |
dc.citation.epage | 47 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000166961800011 | - |
顯示於類別: | 會議論文 |