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dc.contributor.authorChang, YWen_US
dc.contributor.authorLin, JMen_US
dc.contributor.authorWong, DFen_US
dc.date.accessioned2014-12-08T15:27:20Z-
dc.date.available2014-12-08T15:27:20Z-
dc.date.issued1998en_US
dc.identifier.isbn1-58113-008-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/19584-
dc.description.abstractProcess technology advances will soon make the one-million gate FPGA a reality. A key issue that needs to be solved for the large-scale FPGAs to realize their full potential lies in the design of their segmentation architectures [10]. One-dimensional segmentation designs have been studied to some degree in much of the literature; most of the previously proposed methods are based on stochastic or analytical analysis. In this paper, we address a new direction for studying segmentation architectures. Our method is based on graph-theoretic formulation. We first formulate a net matching problem and present a polynomial-time optimal algorithm to solve the problem. Based on the solution to the problem, we develop an effective and efficient matching-based algorithm for FPGA segmentation designs. Experimental results show that our method significantly outperforms previous work. For example, our method achieves averages of 18.2% and 8.9% improvements in routability, compared with the work in [14] and the most recent work in [7] respectively. More importantly, our approaches are very flexible and can readily extend to higher-order segmentation designs (e.g., two- or three-dimensional segmentation design, etc), which are crucial to the design of large-scale FPGAs.en_US
dc.language.isoen_USen_US
dc.titleGraph matching-based algorithms for FPGA segmentation designen_US
dc.typeProceedings Paperen_US
dc.identifier.journal1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERSen_US
dc.citation.spage34en_US
dc.citation.epage39en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000077729800005-
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