標題: An area and time efficient adder for multiple additions with different word-length
作者: Liang, BS
Nieh, YC
Jen, CW
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
公開日期: 1997
摘要: To calculate multiple independent additions with different word-length by hardware sharing, we propose a new adder architecture in this paper, named self carry routing adder (SCRA). Multiple additions for data with different precision are usually occurring in some applications, like DDA operation in 3-D graphics rendering. By segmentation, rearrangement and dynamic carry routing, SCRA design can effectively decrease the delay time, reduce hardware area, and achieve high hardware utilization.
URI: http://hdl.handle.net/11536/19722
ISBN: 0-7803-3583-X
期刊: ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE
起始頁: 2112
結束頁: 2115
Appears in Collections:Conferences Paper