Functional test pattern generation for CMOS operational amplifier

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chang, SJ	en_US
dc.contributor.author	Lee, CL	en_US
dc.contributor.author	Chen, JE	en_US
dc.date.accessioned	2014-12-08T15:27:29Z	-
dc.date.available	2014-12-08T15:27:29Z	-
dc.date.issued	1997	en_US
dc.identifier.isbn	0-8186-7810-0	en_US
dc.identifier.issn	1093-0167	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19751	-
dc.description.abstract	In this paper, the optimum functional patterns for CMOS operational amplifier are proposed based on an analysis to find the maximum difference between the good circuit and the faulty circuit for a CMOS operational amplifier. The theoretical and simulation results show that the derived test patterns do give the maximum difference at the output even when the circuit has a ''soft'' fault. The results have also been applied to generate test patterns for a programmable gain/loss mixed signal circuit.	en_US
dc.language.iso	en_US	en_US
dc.title	Functional test pattern generation for CMOS operational amplifier	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	15TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS	en_US
dc.citation.spage	267	en_US
dc.citation.epage	272	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1997BH73L00038	-
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