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dc.contributor.authorYeh, Kuo-Liangen_US
dc.contributor.authorGuo, Jyh-Chyurnen_US
dc.date.accessioned2014-12-08T15:27:34Z-
dc.date.available2014-12-08T15:27:34Z-
dc.date.issued2011-09-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2011.2158105en_US
dc.identifier.urihttp://hdl.handle.net/11536/19814-
dc.description.abstractThe impact of layout-dependent parasitic capacitances on extraction of inversion carrier density Q(inv) and effective mobility mu(eff) has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the extrinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such as gate finger sidewall and finger-end fringing capacitances, i.e., C(of) and C(f(poly-end)), respectively. Both categories of parasitic capacitance lead to overestimated Q(inv) and underestimated mu(eff). The increase in effective channel width W(eff) due to Delta W from shallow trench isolation (STI) top-corner rounding may compensate mu(eff) degradation due to STI stress. The tradeoff between mu(eff) and W(eff) determines the impact of width scaling on I(DS) and G(m). A new method based on the measured S-parameters, open-M1 deembedding, and Raphael simulation can precisely determine the mentioned parameters associated with the intrinsic channel and realize accurate extraction of mu(eff) in multifinger MOSFETs with various layouts and narrow widths down to 0.125 mu m.en_US
dc.language.isoen_USen_US
dc.subjectEffective mobilityen_US
dc.subjecteffective widthen_US
dc.subjectfringing capacitanceen_US
dc.subjectopen deembeddingen_US
dc.subjectparasitic capacitancesen_US
dc.titleA New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2011.2158105en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume58en_US
dc.citation.issue9en_US
dc.citation.spage2838en_US
dc.citation.epage2846en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000294175900004-
dc.citation.woscount2-
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