標題: Fuzzy-based circuit partitioning in built-in current testing
作者: Tseng, WD
Wang, KC
交大名義發表
資訊工程學系
National Chiao Tung University
Department of Computer Science
公開日期: 1996
摘要: Partitioning a digital circuit into modules before implementing on a single chip is key to balancing between test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistic analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible since IDDQ testing requires the measurement of an analog quantity rather than a digital signal. In this paper, we propose a fuzzy-based approach which provides a soft threshold to determine the module size for BICT partitioning. Evaluation results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning.
URI: http://hdl.handle.net/11536/19923
ISBN: 0-7803-3662-3
期刊: PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997
起始頁: 397
結束頁: 400
顯示於類別:會議論文