Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Tseng, WD | en_US |
| dc.contributor.author | Wang, KC | en_US |
| dc.date.accessioned | 2014-12-08T15:27:39Z | - |
| dc.date.available | 2014-12-08T15:27:39Z | - |
| dc.date.issued | 1996 | en_US |
| dc.identifier.isbn | 0-7803-3662-3 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/19923 | - |
| dc.description.abstract | Partitioning a digital circuit into modules before implementing on a single chip is key to balancing between test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistic analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible since IDDQ testing requires the measurement of an analog quantity rather than a digital signal. In this paper, we propose a fuzzy-based approach which provides a soft threshold to determine the module size for BICT partitioning. Evaluation results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning. | en_US |
| dc.language.iso | en_US | en_US |
| dc.title | Fuzzy-based circuit partitioning in built-in current testing | en_US |
| dc.type | Proceedings Paper | en_US |
| dc.identifier.journal | PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997 | en_US |
| dc.citation.spage | 397 | en_US |
| dc.citation.epage | 400 | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | 資訊工程學系 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.contributor.department | Department of Computer Science | en_US |
| dc.identifier.wosnumber | WOS:A1996BJ06S00066 | - |
| Appears in Collections: | Conferences Paper | |

