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dc.contributor.authorTseng, WDen_US
dc.contributor.authorWang, KCen_US
dc.date.accessioned2014-12-08T15:27:39Z-
dc.date.available2014-12-08T15:27:39Z-
dc.date.issued1996en_US
dc.identifier.isbn0-7803-3662-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/19923-
dc.description.abstractPartitioning a digital circuit into modules before implementing on a single chip is key to balancing between test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistic analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible since IDDQ testing requires the measurement of an analog quantity rather than a digital signal. In this paper, we propose a fuzzy-based approach which provides a soft threshold to determine the module size for BICT partitioning. Evaluation results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning.en_US
dc.language.isoen_USen_US
dc.titleFuzzy-based circuit partitioning in built-in current testingen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997en_US
dc.citation.spage397en_US
dc.citation.epage400en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:A1996BJ06S00066-
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