| 標題: | AN ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER WITH LOW RATIO-SENSITIVITY AND GAIN-SENSITIVITY AND 4N-CLOCK CONVERSION CYCLE |
| 作者: | CHIN, SY WU, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| 公開日期: | 1994 |
| URI: | http://hdl.handle.net/11536/20188 |
| ISBN: | 0-7803-1915-X |
| 期刊: | 1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 5: LINEAR CIRCUITS AND SYSTEMS (LCS) - ANALOG SIGNAL PROCESSING (ASP) |
| 起始頁: | E325 |
| 結束頁: | E328 |
| 顯示於類別： | 會議論文 |
- A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter / Chin, SY;Wu, CY
- A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration / Liu, HC;Lee, ZM;Wu, JT
- 應用於類比數位轉換器之時脈抖動量測與補償技術 / 范啟威;Fan, Chi-Wei;吳介琮;Wu, Jieh-Tsorng
- 可用於低電壓動態電壓與頻率調節系統之多相時脈設計與電壓準位轉換設計 / 陳美維;黃威;Hwang, Wei
- A CMOS TRANSISTOR-ONLY 8-B 4.5-MS/S PIPELINED ANALOG-TO-DIGITAL CONVERTER USING FULLY-DIFFERENTIAL CURRENT-MODE CIRCUIT TECHNIQUES / WU, CY;CHEN, CC;CHO, JJ
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