Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | WANG, KH | en_US |
| dc.contributor.author | HWANG, TT | en_US |
| dc.contributor.author | CHEN, C | en_US |
| dc.date.accessioned | 2014-12-08T15:27:58Z | - |
| dc.date.available | 2014-12-08T15:27:58Z | - |
| dc.date.issued | 1993 | en_US |
| dc.identifier.isbn | 7-80003-275-6 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/20233 | - |
| dc.language.iso | en_US | en_US |
| dc.title | TECHNOLOGY MAPPING FOR FPGA USING GENERALIZED FUNCTIONAL DECOMPOSITION | en_US |
| dc.type | Proceedings Paper | en_US |
| dc.identifier.journal | NEW ADVANCES IN COMPUTER AIDED DESIGN & COMPUTER GRAPHICS, VOLS 1 AND 2 | en_US |
| dc.citation.spage | 605 | en_US |
| dc.citation.epage | 610 | en_US |
| dc.contributor.department | 資訊工程學系 | zh_TW |
| dc.contributor.department | Department of Computer Science | en_US |
| dc.identifier.wosnumber | WOS:A1993BZ61V00116 | - |
| Appears in Collections: | Conferences Paper | |
- Unified functional decomposition via encoding for FPGA technology mapping / Jiang, JH;Jou, JY;Huang, JD
- Compatible class encoding in hyper-function decomposition for FPGA synthesis / Jiang, JHR;Jou, JY;Huang, JD
- ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping / Huang, JD;Jou, JY;Shen, WZ
- A variable partitioning algorithm of BDD for FPGA technology mapping / Jiang, JH;Jou, JY;Huang, JD;Wei, JS
- LOGIC SYNTHESIS FOR FIELD-PROGRAMMABLE GATE ARRAYS / HWANG, TT;OWENS, RM;IRWIN, MJ;WANG, KH
- Technology mapping for FPGAs with composite logic block architectures / Chuang, HH;Shung, CB
- Technology mapping for FPGAs with composite logic block architectures / Chuang, HH;Shung, CB
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