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dc.contributor.authorJian, Guo-Anen_US
dc.contributor.authorChien, Cheng-Anen_US
dc.contributor.authorChen, Peng-Shengen_US
dc.contributor.authorGuo, Jiun-Inen_US
dc.date.accessioned2014-12-08T15:28:14Z-
dc.date.available2014-12-08T15:28:14Z-
dc.date.issued2012-10-01en_US
dc.identifier.issn0916-8532en_US
dc.identifier.urihttp://dx.doi.org/10.1587/transinf.E95.D.2505en_US
dc.identifier.urihttp://hdl.handle.net/11536/20444-
dc.description.abstractThis paper proposes a verification-aware design methodology that provides developers with a systematic and reliable approach to performing thread-pipelining parallelization on sequential programs. In contrast to traditional design flow, a behavior-model program is constructed before parallelizing as a bridge to help developers gradually leverage the technique of thread-pipelining parallelization. The proposed methodology integrates verification mechanisms into the design flow. To demonstrate the practicality of the proposed methodology, we applied it to the parallelization of a 3D depth map generator with thread pipelining. The parallel 3D depth map generator was further integrated into a 3D video playing system for evaluation of the verification overheads of the proposed methodology and the system performance. The results show the parallel system can achieve 33.72 fps in D1 resolution and 12.22 fps in HD720 resolution through a five-stage pipeline. When verifying the parallel program, the proposed verification approach keeps the performance degradation within 23% and 21.1% in D1 and HD720 resolutions, respectively.en_US
dc.language.isoen_USen_US
dc.subjectverificationen_US
dc.subject3D depth map generationen_US
dc.subjectpipelineen_US
dc.subjectparallel computingen_US
dc.subjectbehavior modelen_US
dc.titleA Verification-Aware Design Methodology for Thread Pipelining Parallelizationen_US
dc.typeArticleen_US
dc.identifier.doi10.1587/transinf.E95.D.2505en_US
dc.identifier.journalIEICE TRANSACTIONS ON INFORMATION AND SYSTEMSen_US
dc.citation.volumeE95Den_US
dc.citation.issue10en_US
dc.citation.spage2505en_US
dc.citation.epage2513en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000310397700014-
dc.citation.woscount0-
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