完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Jian, Guo-An | en_US |
dc.contributor.author | Chien, Cheng-An | en_US |
dc.contributor.author | Chen, Peng-Sheng | en_US |
dc.contributor.author | Guo, Jiun-In | en_US |
dc.date.accessioned | 2014-12-08T15:28:14Z | - |
dc.date.available | 2014-12-08T15:28:14Z | - |
dc.date.issued | 2012-10-01 | en_US |
dc.identifier.issn | 0916-8532 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1587/transinf.E95.D.2505 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/20444 | - |
dc.description.abstract | This paper proposes a verification-aware design methodology that provides developers with a systematic and reliable approach to performing thread-pipelining parallelization on sequential programs. In contrast to traditional design flow, a behavior-model program is constructed before parallelizing as a bridge to help developers gradually leverage the technique of thread-pipelining parallelization. The proposed methodology integrates verification mechanisms into the design flow. To demonstrate the practicality of the proposed methodology, we applied it to the parallelization of a 3D depth map generator with thread pipelining. The parallel 3D depth map generator was further integrated into a 3D video playing system for evaluation of the verification overheads of the proposed methodology and the system performance. The results show the parallel system can achieve 33.72 fps in D1 resolution and 12.22 fps in HD720 resolution through a five-stage pipeline. When verifying the parallel program, the proposed verification approach keeps the performance degradation within 23% and 21.1% in D1 and HD720 resolutions, respectively. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | verification | en_US |
dc.subject | 3D depth map generation | en_US |
dc.subject | pipeline | en_US |
dc.subject | parallel computing | en_US |
dc.subject | behavior model | en_US |
dc.title | A Verification-Aware Design Methodology for Thread Pipelining Parallelization | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1587/transinf.E95.D.2505 | en_US |
dc.identifier.journal | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS | en_US |
dc.citation.volume | E95D | en_US |
dc.citation.issue | 10 | en_US |
dc.citation.spage | 2505 | en_US |
dc.citation.epage | 2513 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000310397700014 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |