標題: | Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors |
作者: | Li, Yiming Lee, Jam-Wem Chou, Hung-Mu 電子物理學系 友訊交大聯合研發中心 Department of Electrophysics D Link NCTU Joint Res Ctr |
關鍵字: | strained silicon;nanowire FET;surrounding-gate;drain induced barrier height lowering;threshold-voltage roll-off;gate capacitance;simulation |
公開日期: | 1-十月-2004 |
摘要: | In this paper we numerically examine the electrical characteristics of surrounding-gate strained silicon nanowire field effect transistors (FETs) by changing the radius (RSiGe) of silicon-germanium (SiGe) wire. Due to the higher electron mobility, the n-type FETs with strained silicon channel films do enhance driving capability (similar to 8% increment on the drain current) in comparison with the pure Si one. The leakage current and transfer characteristics, the threshold-voltage (V-t), the drain induced barrier height lowering (DIBL), and the gate capacitance (C-G) are estimated with respect to different gate length (L-G), gate bias (V-G), and R-SiGe. For short channel effects, such as V-t roll-off and DIBL, the surrounding-gate strained silicon nanowire FET sustains similar characteristics with the pure Si one. |
URI: | http://dx.doi.org/10.1007/s10825-004-7056-7 http://hdl.handle.net/11536/20513 |
ISSN: | 1569-8025 |
DOI: | 10.1007/s10825-004-7056-7 |
期刊: | JOURNAL OF COMPUTATIONAL ELECTRONICS |
Volume: | 3 |
Issue: | 3-4 |
起始頁: | 251 |
結束頁: | 255 |
顯示於類別: | 期刊論文 |