標題: Low-Spur Technique For Integer-N Phase-Locked Loop
作者: Liao, Te-Wen
Su, Jun-Ren
Hung, Chung-Chih
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: PLL;low spur;Synthesizer
公開日期: 2012
摘要: In this paper, we presents a low-spur phase locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator (VCO) in order to reduce the reference spur at the output of the PLL. A new random clock generator is presented to perform a random selection of phase frequency detector (PFD) control for charge pump at locked state. The proposed frequency synthesizer was fabricated in TSMC 0.18-mu m CMOS process. The PLL has achieved the phase noise of -105 dBc/Hz at 1MHz offset frequency and reference spurs below -72dBc.
URI: http://hdl.handle.net/11536/20750
ISBN: 978-1-4673-2527-1
ISSN: 1548-3746
期刊: 2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)
起始頁: 546
結束頁: 549
Appears in Collections:Conferences Paper