| 標題: | Electrical Performances and Quality Investigations of Integrated Bonded Structures and TSVs for 3D Interconnects |
| 作者: | Chen, K. N. Chang, Y. J. Ko, C. T. Hsu, S. Y. Chen, H. Y. Hsiao, C. Yu, T. H. Chen, Y. H. Lo, W. C. 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| 公開日期: | 2012 |
| URI: | http://hdl.handle.net/11536/20752 |
| ISBN: | 978-1-4673-1137-3 |
| 期刊: | 2012 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC) |
| 顯示於類別： | 會議論文 |
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- Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding / Chen, K. N.;Shaw, T. M.;Cabral, C., Jr.;Zuo, G.
- Electrical and Reliability Investigation of Cu TSVs With Low-Temperature Cu/Sn and BCB Hybrid Bond Scheme / Chang, Yao-Jen;Ko, Cheng-Ta;Chen, Kuan-Neng
- Electrical Performance and Reliability Investigation of Cosputtered Cu/Ti Bonded Interconnects / Chen, Hsiao-Yu;Hsu, Sheng-Yao;Chen, Kuan-Neng
- A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application / Ko, Cheng-Ta;Hsiao, Zhi-Cheng;Chang, Yao-Jen;Chen, Peng-Shu;Hwang, Yu-Jiau
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