完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | YEH, CF | en_US |
dc.contributor.author | YANG, TZ | en_US |
dc.contributor.author | CHEN, TJ | en_US |
dc.date.accessioned | 2014-12-08T15:03:33Z | - |
dc.date.available | 2014-12-08T15:03:33Z | - |
dc.date.issued | 1995-02-01 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/16.370064 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/2081 | - |
dc.description.abstract | As the passivation layer on the top of undoped offset region for offset-gate structured poly-Si TFTs is exposed to hydrogen plasma, a lightly-doped-like drain region could be equivalently self-induced. The hydrogenated polycrystalline silicon thin-film transistor of this structure, named self-induced Lightly-doped-drain (SI-LDD) poly-Si TFTs, was first developed with liquid-phase deposition oxide as both the gate insulator and the passivation layer. This paper describes the optimum hydrogenation condition, and the electrical characteristics for the novel SI-LDD poly-Si TFTs. The effects of DC electrical stress on SI-LDD poly-Si TFTs are also described. Finally a model is proposed to explain the degradation phenomena observed in our SI-LDD devices. | en_US |
dc.language.iso | en_US | en_US |
dc.title | CHARACTERISTICS OF SELF-INDUCED LIGHTLY-DOPED-DRAIN POLYCRYSTALLINE SILICON THIN-FILM TRANSISTORS WITH LIQUID-PHASE DEPOSITION SIO2 AS GATE-INSULATOR AND PASSIVATION-LAYER | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/16.370064 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.citation.volume | 42 | en_US |
dc.citation.issue | 2 | en_US |
dc.citation.spage | 307 | en_US |
dc.citation.epage | 314 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1995QD76800016 | - |
dc.citation.woscount | 19 | - |
顯示於類別: | 期刊論文 |