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dc.contributor.authorChai, Yunen_US
dc.contributor.authorWu, Jieh-Tsorngen_US
dc.date.accessioned2014-12-08T15:28:51Z-
dc.date.available2014-12-08T15:28:51Z-
dc.date.issued2012-12-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JSSC.2012.2217872en_US
dc.identifier.urihttp://hdl.handle.net/11536/20844-
dc.description.abstractA 10-bit 200-MS/s pipelined ADC was fabricated using a standard 65 nm CMOS technology. We propose a dual-path amplification technique for residue generation. We split the pipeline stage into a coarse-stage multiplying digital-to-analog converter (MDAC) and a fine-stage MDAC. The opamps for these two MDACs require different specifications. They can be designed and optimized separately. They are turned off when not in use to save power. We modify the operation of a pipeline stage to accommodate the dual-path scheme by using time-interleaving capacitor sets. Operating at 200 MS/s sampling rate, this ADC consumes 5.37 mW from a 1 V supply. It achieves a signal-to-noise-plus-distortion ratio (SNDR) better than 55 dB SNDR over the entire Nyquist band. The chip active area is 0.19 mm(2).en_US
dc.language.isoen_USen_US
dc.subjectAnalog-to-digital conversionen_US
dc.subjectpipeline processingen_US
dc.subjectswitched-capacitor amplificationen_US
dc.subjectswitching circuitsen_US
dc.titleA CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADCen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JSSC.2012.2217872en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume47en_US
dc.citation.issue12en_US
dc.citation.spage2905en_US
dc.citation.epage2915en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000312829900006-
dc.citation.woscount0-
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