低功率管線式類比數位轉換器

Abstract

近來，隨著高速與高整合電路應用。 先進製程演變趨於更低通道長度與更薄閘極氧化層厚度的 MOS 電晶體製作， 致使電晶體本質增益降低且工作電壓也隨之下降。 類比數位轉換器也對應需與數位處理系統整合在同一顆晶片上 (SOC)。 可操作於低電源電壓且耗電量極小之類比數位轉換器， 即成現今高整合之混合式訊號裝置中最主要的探討課題。\\

管線式類比數位轉換器是目前混合訊號裝置中，主流的產品之一。大多應用在高速與高精確度 兼顧的領域，如移動式通訊系統中之無線區域網路(WLAN)、消費產品中的手機、高解析數位 電視、可攜式電腦等。本論文旨在發展一創新之架構，希望在兼顧高速與高解析度之需求下， 卻可大幅降低其功率消耗。此創新架構在系統與電路上皆有別傳統作法。\\

改良之管線式類比數位轉換器使用雙路架構利用兩路皆不甚精確電路，產生所需精準度之訊號 值。憑藉大量降低電路所需精確度，以達成低耗電與低電壓操作目的。 雙路放大技巧可使電路的功率消耗達到最佳化。 粗定義級 (coarse stage) 的放大器提供訊號所需的大振幅輸出;精確級 (fine stage) 的放大器則將用高精確度的規格，來處理粗定義級的輸出與理想值之間的小振幅誤差值 (residue)。時序交錯式電容也利用在MDAC運作中，用以延長可用之放大時間，減低功率消耗。 此外，本論文亦使用一雙路架構的放大器。 藉由前饋與電流比值方法，透過調整電路極零點位置，實現一個不需電容補償即可達高直流增 益之放大器。進而並行此種雙路放大器架構與切換式放大器的技巧，應用於前述之雙路管線式 類比數位轉換器電路中。藉由雙路管線式類比數位轉換器之特殊結構，可將此放大器設計在非 一般規格下，由此達到一更長足之低耗電值。\\

此電路系統使用65奈米CMOS標準製程技術設計。 電源電壓為 1~V，輸入訊號振幅達 1.3~$V_{pp}$，解析度10位元，最高取樣頻率200MS/s。 於Nyquist取樣頻率下，最大耗電量5.37mW。

With recent application on higher speed and higher integration capability of circuits; the trend is that the channel length of MOS transistor is smaller and the thickness of gate oxide also becomes thinner. Therefore, the intrinsic gain of MOS transistor is lower and the operation voltage is also reduced. By the demand of integrating analog-to-digital con- verter with digital signal-processing system on one chip (SOC), a low-power low-voltage analog-to-digital converter is an important key factor in mixed signal system nowadays. Pipelined analog-to-digital converter is one of the most popular products in mixed- mode signal devices and instruments. Mainly applied in achieving high linearity and high accuracy simultaneously, such as WLAN in mobile communication systems ? cell phone ? HDTV ? portable computer and so on. A novel pipelined ADC structure is developed in this thesis. This work demonstrates the power efficiency when achieving high speed and high accuracy potential of pipelined ADC at the same time. This novel scheme is iiidifferent from conventional works both in system and circuits. The improved Pipelined analog-to-digital converter adopts a dual-path structure. It utilizes two separated analog-to-digital converter paths with inaccurate specifications to generate an equivalent high accurate signal value. By a large reducing of the accuracy required in this novel structure will achieve a low-power and low-voltage implement what we explore. The power is optimized by using dual path amplification technique. The coarse amplifier covers large swing, and fine amplifier handles residue with high preci- sion. Also, time-interleaving capacitor sets are utilized to increase amplification time of MDAC operation for power reducing. Furthermore, a dual-path opamp circuit is also used in this design. By utilizing the methods of feedforward and current-ratio to well place the pole and zero can realize an opamp with high dc gain and eliminate the com- pensation capacitor results in a low power design. Then, we employ this dual-path opamp incorporating with switched opamp technique in the dual-path pipelined analog-to-digital converter what we mentioned above. To make matters even more exciting, by the particu- lar structure of dual-path pipelined analog-to-digital converter, we can design this opamp under unusual specifications to attain to an attractive lower power value. This complete circuit is designed with a 65nm CMOS technology. Power supply volt- age is 1 V, input signal amplitude is 1.3 V pp , resolution is 10-bit, the maximum sampling frequency is 200MS/s. At Nyquist rate, the maximum power consumption is 5.37mW.