完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liao, Yuan-Hsin | en_US |
dc.contributor.author | Li, Gwo-Long | en_US |
dc.contributor.author | Chang, Tian-Sheuan | en_US |
dc.date.accessioned | 2014-12-08T15:29:01Z | - |
dc.date.available | 2014-12-08T15:29:01Z | - |
dc.date.issued | 2012-11-01 | en_US |
dc.identifier.issn | 1051-8215 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCSVT.2012.2202081 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/20931 | - |
dc.description.abstract | To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based adaptive variable length coding (CAVLC) decoder with 21% shorter critical path delay in comparison to the traditional two-level decoder design. Furthermore, redundant decoding processes are removed by a skipping mechanism. The proposed CAVLC decoder only needs 127.13 cycles per macroblock on average to support level 5.1 decoding with 13.54 k gate counts under 90-nm CMOS technology. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Context-adaptive variable length decoder (CAVLD) | en_US |
dc.subject | H.264 | en_US |
dc.title | A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCSVT.2012.2202081 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY | en_US |
dc.citation.volume | 22 | en_US |
dc.citation.issue | 11 | en_US |
dc.citation.spage | 1604 | en_US |
dc.citation.epage | 1610 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000313971700007 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |