完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen, Chun-Yen | en_US |
dc.contributor.author | Peng, Ruei Hong | en_US |
dc.contributor.author | Tsai, Jen-Chieh | en_US |
dc.contributor.author | Kang, Yu-Chi | en_US |
dc.contributor.author | Ni, Chia-Lung | en_US |
dc.contributor.author | Chen, Yi-Ting | en_US |
dc.contributor.author | Chen, Ke-Horng | en_US |
dc.contributor.author | Wang, Shih-Ming | en_US |
dc.contributor.author | Lee, Ming-Wei | en_US |
dc.contributor.author | Luo, Hsin-Yu | en_US |
dc.date.accessioned | 2014-12-08T15:29:03Z | - |
dc.date.available | 2014-12-08T15:29:03Z | - |
dc.date.issued | 2012 | en_US |
dc.identifier.isbn | 978-1-4673-0801-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/20951 | - |
dc.description.abstract | the proposed interleaving power factor correction (PFC) can effectively reduce the size of the AC-DC converter for portable electronics. Fully integrated variable sampling slope (VSS) technique can provide precise phase regulation under variable line voltage. Besides, the no-deadtime ramp generator (NDRG) records the previous status to modify the sequent on-time value to achieve current sharing for suppressing the total harmonic distortion (THD) and restraining the input current ripple, EMI filter, and the size of input inductor. Therefore, more power can be provided by the proposed interleaving PFC than that of single-phase PFC. Simultaneously, the drawback of the peak current twice than the average current in the Boundary control mode (BCM) can be greatly reduced. The test circuit fabricated in the TSMC 0.5 mu m 800V UHV process shows the highly integrated interleaving PFC can deliver high power of 180W with improved phase regulation precision. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | variable sampling slope (VSS) | en_US |
dc.subject | no-deadtime ramp generator (NDRG) | en_US |
dc.subject | power factor correction (PFC) | en_US |
dc.subject | boundary control mode (BCM) | en_US |
dc.subject | interleaving | en_US |
dc.title | Variable Sampling Slope (VSS) and No-Deadtime Ramp Generator (NDRG) Techniques for Closed-Loop Interleaving Power Factor Correction (PFC) Design with Suppression of Current Mismatch | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2012 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE) | en_US |
dc.citation.spage | 298 | en_US |
dc.citation.epage | 301 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000312901700042 | - |
顯示於類別: | 會議論文 |