標題: | Compact and Low-Loss ESD Protection Design for V-Band RF Applications in a 65-nm CMOS Technology |
作者: | Chu, Li-Wei Lin, Chun-Yu Tsai, Shiang-Yu Ker, Ming-Dou Song, Ming-Hsiang Jou, Chewn-Pu Lu, Tse-Hua Tseng, Jen-Chou Tsai, Ming-Hsien Hsu, Tsun-Lai Hung, Ping-Fang Chang, Tzu-Heng 交大名義發表 National Chiao Tung University |
關鍵字: | Electrostatic discharge (ESD);radio frequency (RF);V band |
公開日期: | 2012 |
摘要: | Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area. |
URI: | http://hdl.handle.net/11536/21577 |
ISBN: | 978-1-4673-0219-7 |
ISSN: | 0271-4302 |
期刊: | 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) |
起始頁: | 2127 |
結束頁: | 2130 |
Appears in Collections: | Conferences Paper |