標題: RESIDUE SYSTOLIC IMPLEMENTATIONS FOR NEURAL NETWORKS
作者: ZHANG, CN
WANG, M
TSENG, CC
資訊工程學系
Department of Computer Science
關鍵字: MIXED-RADIX CONVERSION;NEURAL NETWORK;PARALLEL PROCESSING;RESIDUE NUMBER SYSTEM;SYSTOLIC ARRAY
公開日期: 1995
摘要: In this work we propose two techniques for improving VLSI implementations for artificial neural networks (ANNs). By making use of two kinds of processing elements (PEs), one dedicated to the basic operations (addition and multiplication) and another to evaluate the activation function, the total time and cost for the VLSI array implementation of ANNs can be decreased by a factor of two compared with previous work. Taking the advantage of residue number system, the efficiency of each PE can be further increased. Two RNS-based array processor designs are proposed. The first is built by look-up tables, and the second is constructed by binary adders accomplished by the mixed-radix conversion (MRC), such that the hardwares are simple and high speed operations are obtained. The proposed techniques are general enough to be extended to cover other forms of loading and learning algorithms.
URI: http://hdl.handle.net/11536/2157
http://dx.doi.org/10.1007/BF01414076
ISSN: 0941-0643
DOI: 10.1007/BF01414076
期刊: NEURAL COMPUTING & APPLICATIONS
Volume: 3
Issue: 3
起始頁: 149
結束頁: 156
Appears in Collections:Articles