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dc.contributor.authorYang, Hao-Yuen_US
dc.contributor.authorLin, Chen-Weien_US
dc.contributor.authorChen, Hung-Hsinen_US
dc.contributor.authorChao, Mango C. -T.en_US
dc.contributor.authorTu, Ming-Hsienen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2014-12-08T15:30:07Z-
dc.date.available2014-12-08T15:30:07Z-
dc.date.issued2012en_US
dc.identifier.isbn978-1-4673-1595-1en_US
dc.identifier.issn1089-3539en_US
dc.identifier.urihttp://hdl.handle.net/11536/21588-
dc.description.abstractDue to the increasing demands of lower-power devices, a lot of research effort has been devoted to develop new SRAM cell designs that can be effectively and economically operated at the subthreshold region. However, each new SRAM cell design has its own cell structure and design techniques, which may result in different faulty behaviors than the conventional 6T SRAMs and require specialized test methods to detect those uncovered fault models. In this paper, we focus on developing the test methods for testing a new 9T subthreshold SRAM design, which utilizes single bit-line read/write, two write word-lines for writing different values, and a separate read path. A mixed march algorithm with different background and address-traverse directions is proposed to detect various uncovered fault models and validated through real test chips. A new specialized technique of floating bit-line attacking is also presented to detect the stability faults, which cannot be effectively detected by applying the conventional test methods, for the new 9T SRAM design.en_US
dc.language.isoen_USen_US
dc.titleTesting Strategies for a 9T Sub-threshold SRAMen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS INTERNATIONAL TEST CONFERENCE 2012en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000316569200046-
Appears in Collections:Conferences Paper