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dc.contributor.authorLiu, Wen-Haoen_US
dc.contributor.authorKao, Wei-Chunen_US
dc.contributor.authorLi, Yih-Langen_US
dc.contributor.authorChao, Kai-Yuanen_US
dc.date.accessioned2014-12-08T15:30:13Z-
dc.date.available2014-12-08T15:30:13Z-
dc.date.issued2013-05-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCAD.2012.2235124en_US
dc.identifier.urihttp://hdl.handle.net/11536/21646-
dc.description.abstractModern global routers employ various routing methods to improve routing speed and quality. Maze routing is the most time-consuming process for existing global routing algorithms. This paper presents two bounded-length maze routing (BLMR) algorithms (optimal-BLMR and heuristic-BLMR) that perform much faster routing than traditional maze routing algorithms. In addition, a rectilinear Steiner minimum tree aware routing scheme is proposed to guide heuristic-BLMR and monotonic routing to build a routing tree with shorter wirelength. This paper also proposes a parallel multithreaded collision-aware global router based on a previous sequential global router (SGR). Unlike the partitioning-based strategy, the proposed parallel router uses a task-based concurrency strategy. Finally, a 3-D wirelength optimization technique is proposed to further refine the 3-D routing results. Experimental results reveal that the proposed SGR uses less wirelength and runs faster than most of other state-of-the-art global routers with a different set of parameters [12], [16], [17], [20]. Compared to the proposed SGR, the proposed parallel router yields almost the same routing quality with average 2.71 and 3.12-fold speedup on overflow-free and hard-to-route cases, respectively, when running on a 4-core system.en_US
dc.language.isoen_USen_US
dc.subjectglobal routingen_US
dc.subjectmaze routingen_US
dc.subjectmultithreaded routingen_US
dc.subjectphysical designen_US
dc.subjectrip-up and rerouteen_US
dc.titleNCTU-GR 2.0: Multithreaded Collision-Aware Global Routing with Bounded-Length Maze Routingen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCAD.2012.2235124en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume32en_US
dc.citation.issue5en_US
dc.citation.spage709en_US
dc.citation.epage722en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000318163800005-
dc.citation.woscount4-
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